1. Field of the Invention
This invention relates to a code conversion circuit, and more particularly to a flash type AD converter of monolithic IC structure operable at a high speed.
2. Description of the Prior Art
A flash type AD converter includes a plurality of comparators operating in parallel to each other for deciding the level of its input signal, and an output pattern of the comparator group is converted into a signal coded according to a desired code. Although the conversion rate of AD converters of this type commonly ranges from several-ten MHz to several-hundred MHz, the bandwidth of their inputs is limited to frequencies far lower than the above range in most of these AD converters. When an input signal having a frequency exceeding the above limit is applied to the flash type AD converter, a missing code attributable to nonuniformity of response speeds of individual comparators tends to occur. When such a missing code occurs, the value of the digital output signal of the AD converter can no longer be guaranteed.
An example of a flash type AD converter having means for preventing occurrence of such a missing code is disclosed in JP-A-59-107629 (1984). The disclosed AD converter includes, as encoders converting output patterns of plural comparators into binary signals, a plurality of primary stage encoders generating predetermined less significant bits of the binary signals and a single final stage encoder receiving the outputs of these primary stage encoders to generate all of the bits of the binary signals. The disclosed AD converter further includes gate circuits inserted in bit output lines leading from the individual primary stage encoders to the final stage encoder as means for preventing occurrence of a missing code, and a signal representing the logical sum of binary outputs generated from the primary stage encoders of higher order and appearing on the individual bit output lines is applied to the gate circuits as an inhibit signal. Therefore, simultaneous generation of binary outputs from the plural primary stage encoders is prevented, so that the occurrence of a missing code due to simultaneous double appearance of outputs from the unit circuit blocks, each including one of the primary stage encoders, can be prevented.
However, in such a missing code preventive circuit, the size of the circuit blocks gated by the inhibit signal has been determined by the number of the comparators that can be connected to each of the individual primary stage encoders due to the chip layout. Also, when the frequency of the input signal applied to the AD converter is very high, the plural comparators in the circuit block may simultaneously generate their outputs. Therefore, with such a missing code preventive circuit, there has been a limitation in the effect for raising the limit of the input bandwidth. Further, because of the necessity for provision of OR gates to obtain the OR signal described above, the missing code preventing circuit has inevitably occupied a relatively large area on the semiconductor chip.